A monolithic Integrated Circuit (IC) includes multiple active devices built on a semiconductor substrate. Unintended parasitic devices are also formed which can result in undesirable crosstalk between devices. A CMOS integrated circuit built on a P-substrate often include a parasitic NPN transistor formed from the P-substrate, an N-well and another N region. Latch-up of the integrated circuit can occur when a PNPN structure formed due to the parasitic NPN transistor becomes triggered.
Latch-up can be a particularly serious problem for power integrated circuits incorporating high voltage switching devices and nominal voltage controller circuitry. Transient voltages during the switching of a power device on the power integrated circuit can end up forward biasing the emitter and base junction of the parasitic NPN transistor, resulting in injection of minority carriers into the substrate. Guard ring structures, which can be biased or unbiased, have been used to isolate a device or a circuit that introduces parasitic current in an integrated circuit. Guard ring structures are used to collect the undesired minority carriers injected into the substrate. For example, a guard ring is often used to surround an LDMOS transistor to collect minority carriers and to prevent latch-up.
Conventional guard ring structures are usually space consuming, requiring a large silicon area to implement. FIG. 1 illustrates a conventional double guard ring structure surrounding an active device. FIG. 2 is a cross-sectional view of the conventional double guard ring structure of FIG. 1 along the line A-A′. Referring to FIGS. 1 and 2, an integrated circuit 10 is formed on a P-substrate 12 with a P-type epitaxial layer 14 formed thereon. The conventional guard ring structure 16 typically includes an N-type guard ring formed by a deep N-well 20 surrounded on all sides by a P-type guard ring formed by a P-well 24. An N-well 18 may be formed in the deep N-well 20. The guard ring structure 16 surrounds the active device 22 to be protected. For example, the active device may be an N-type LDMOS transistor formed on an N-type buried layer 26. The N-type guard ring of the guard ring structure 16 collects minority carriers (electrons) that may be injected into the substrate 12 by the LDMOS transistor device 22. The P-type guard ring of the guard ring structure 16 further collects majority carriers (holes) that may be generated when electrons injected recombine before they get collected by the N-well 20.
In the case that the active device to be protected is formed on the edge of the integrated circuit, the guard ring may be formed in an U-shape to surround the inward facing sides of the active device 22, as shown in FIG. 1. The N-type guard ring (N-well/deep N-well 18, 20) may be left floating or connected to either the ground potential or connected to the positive power supply Vdd. N+ diffusion regions 30 are formed in the N-well/deep N-well to form ohmic contact with overlying contacts (not shown) and to reduce the well resistance. The P-type guard ring (P-well 24) is typically connected to ground using P+ diffusion regions to form ohmic contact with overlying contacts (not shown), also referred to as P-taps. In some cases, the P-wells of the P-type guard ring closer to the active device may be left floating while the P-wells of the P-type guard ring on the other side of the N-type guard ring may be connected to ground. As thus constructed, a parasitic NPN bipolar transistor is formed with the N-type guard ring as the collector, the substrate 12 as the base and the N-buried layer in the active device 22 as the emitter.
The conventional guard ring structure is space consuming, increasing the die size and the cost of the integrated circuit. In particular, the minimum spacing required between the P-type buried layer (PBL) 28 of the P-well 24 and the N-type buried layer (NBL) 26 of the N-type guard ring increases the silicon area required for implementing the guard ring structure.